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Currently, we can offer silicon proven 10-bits/12-bits Pipeline ADC, PLL, DLL, and DDRII at TSMC65GP process. And we also can design the IP as customer special requirement.
 
In our road map, our interface IP will include USB3.0/USB2.0 PHY and controller, PCI Express 3.0, SATA2/3, SERDES, HDMI and LVDS etc. The USB3.0/USB2.0 PHY will be taped out in Sep. 2011, PCI Express 3.0 will be taped out in Dec.2011.


Our analog and mixed-signal IP will include Audio CODEC, 14bits 160MHz Pipeline ADC, 10bits 300MHz Pipeline ADC, 10bits 500MHz DAC, 400MHz to 5GHz SSC PLL. Audio CODEC, 14 bits Pipeline ADC and PLL will be taped out in Dec. 2011.
 

Our Embedded Memories/ Standard Cells/ GPIO library will be manufactured at 40nm first, The first version of Embedded SRAM will be 8M bits at 500MHz and will be taped out in Dec. 2011.

 

Qualchip in-house IP availability:

 

Analog and Mixed Signal IP
   

    ADC/DAC
   10-bits 240MHz Pipeline ADC : silicon proven
   12-bits 160MHz Pipeline ADC : silicon proven
   14-bits 100MHz Pipeline ADC:  under construction
  

    PLL/DLL
   200MHz-800MHz DLL:             silicon proven
   200MHz-2.6GHz SSC PLL:      silicon proven
  

    High Speed Interface
   1066MHz DDRII PHY:              silicon proven
   1333MHz DDRII/III PHY:           under construction

 

 

 

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